As the design improvements and manufacturing capabilities of integrated circuits and electronic components continues to progress, the speed at which systems process data also increases. The increased data processing capabilities of electronic systems has led to the need for memory devices that can provide as much data at as high a rate as possible. Increased data transmission rates (data bandwidth) have been achieved using a number of approaches. One approach has been to increase the data word size of the system (i.e., the number of bits accessed in a given read or write operation). Such approaches can be limiting, as wider words require wider system buses, which can increase the overall physical size of the system. Another approach is to increase the rate at which read operations can take place (i.e., increase the speed at which data can be read from or written to a memory device). A third way to increase data bandwidth is to increase the efficiency with which a data bus is utilized. Increased bus efficiency has given rise to synchronous systems.
Synchronous systems typically include a number of devices that operate in synchronism with a system clock. For example, a synchronous system would include a synchronous memory device that can be configured to provide output data on a predetermined number of clock cycles following the application of an address. Thus, data processing devices that read data from such a memory device (such as a microprocessor, or the like) do not have to monopolize the data bus following a read command, as the data processing device will essentially "know" when the data will be available. For even more efficient transfer of data, a synchronous memory device can include a burst mode in which data accesses (read operations or write operations) can occur on consecutive cycles of the system clock.
A common type of synchronous memory device is the synchronous random access memory (RAM). In a typical synchronous RAM, address and command inputs are latched on the rising edge of the system clock signal. In the same fashion, input data are latched, or output data are provided in synchronism with the system clock. In order to ensure accurate timing of such operations, it is important that the synchronous RAM be able to receive the system clock signal, and distribute it internally to various circuits within, including input latches and output buffers.
In a conventional synchronous system the various operations of devices within the system are timed off the rising edge of the system clock. Accordingly, conventional synchronous RAMs are expected to latch address data, command data, and input data, and to provide output data on the rising edge of the system clock. Such synchronous operations are usually achieved by a clock circuit within the synchronous RAM that buffers the system clock signal, and distributes it to the other circuits of the synchronous RAM. The other circuits within the synchronous RAM are designed to be activated on the rising edge of the internal clock. In order to compensate for propagation delays of timing signals, the synchronous RAM may include a phase locked loop circuit (PLL) or a delay locked loop circuit (DLL) to shift the phase of internal timing signals.
The desire to provide faster speed systems has given rise to double data rate (DDR) devices. DDR devices typically operate in synchronism with the rising edge of the system clock, and in addition, with the rising edge of an inverse system clock. The use of such "differential" clock signals allows the DDR devices to essentially operate at twice the system clock frequency.
Referring now to FIG. 1, an example of a DDR synchronous RAM is set forth in a block schematic diagram. The DDR RAM is designated by the general reference character 100 and shown to include a memory cell array 102 having a number of memory cells that are accessed by a row select circuit 104, and a input/output (I/O) path circuit 106. When activated, the row select and I/O path circuits (104 and 106) access memory cells according to a row address (ROWADD) and a column address (COLADD). The row and column addresses (ROWADD and COLADD) are provided by an address buffer 108. The address buffer 108, row select circuit 104, and I/O path circuit 106 are each activated by timing signals provided from a timing and control circuit 110.
The timing and control circuit 110 receives differential clock signals, shown as CLK and /CLK, and a number of control signals, shown as CTRL. In addition, the timing and control circuit 110 receives a reference signal REF from a reference circuit 112. In response to the various inputs, the timing and control circuit 110 provides address control signals ADDCTRL, row control signals RCTRL, column control signals CCTRL, and I/O control signals I/OCTRL. The ADDCTRL signals activate the address buffer 108, latching address data. The RCTRL signals activate the row select circuit 104, resulting in the selection of a row of memory cells within the array of memory cells 102. The column control signals CCTRL activate a column select circuit 114 within the I/O path circuit 106, resulting in access to selected columns of the array of memory cells 102. The I/O CTRL signals activate an I/O buffer 116 within the I/O path circuit, resulting in the latching of input data or the driving of output data on a number of data I/Os 118. It is understood that the ADDCTRL, RCTRL, CCTRL and I/OCTRL signals can all be synchronous with the CLK and /CLK signals.
Referring now to FIG. 2, a block schematic diagram is set forth illustrating the timing and control circuit, shown as 110 in FIG. 1. The timing and control circuit is designated by the general reference character 200, and is shown to include a first differential clock receiver 202, a second differential clock receiver 204 and a control logic circuit 206. The first differential clock receiver 202 receives the system clock signal CLK and the reference signal REF. The first differential clock receiver 202 compares the CLK signal with the REF signal to generate an internal clock signal CLKI. In a similar fashion, the second differential clock receiver 204 compares the /CLK signal with the reference signal REF to generate an internal inverse clock signal /CLKI. The CLKI and /CLKI signals, in addition to the CTRL signals, are coupled to the control logic circuit 206. In response to the control signals CTRL, the control logic circuit 206 activates the ADDCTRL, RCTRL, CCTRL and I/OCTRL signals in synchronism with the CLKI and /CLKI signals.
FIG. 3 is provided to illustrate the first and second differential clock receivers (202 and 204). The differential clock receivers (202 and 204) are amplifier circuits that amplify the difference between the REF signal and the clock signal receives (CLK or /CLK). The clock receivers (202 and 204) are necessary as the clock signals received by the synchronous RAMs (CLK or /CLK) may not be ideal.
To better illustrate the operation of the synchronous memory device of FIGS. 1 and 2, a timing diagram is set forth in FIG. 4. The timing diagram includes a number of timing signals including a system clock signal CLKS, an inverse system clock signal /CLKS, a received clock signal CLK, a received inverse clock signal /CLK, a reference signal REF, a resulting internal clock signal CLKI, a resulting inverse internal clock signal /CLKI, and a sample data input signal DQ. The system clock signals (CLKS and /CLKS) represent the differential clock signals as they appear at the system clock source, and so are have an ideal form (a generally square wave shape). The received differential clock signals (CLK and /CLK) represent the resulting non-ideal clock signals received by the synchronous memory device. The non-ideal response can result from the impedance, noise, and transmission line effects on the lines carrying the differential clock signals.
In FIG. 4, the REF signal is shown superimposed over the CLK and /CLK signals. The CLK and /CLK signals are shown to both transition between logic high value and a logic low value, with the /CLK clock being the general inverse of the CLK signal. The REF signal is shown to be about midway between the logic high and logic low level. By operation of the differential clock receivers (202 and 204), when the CLK signal is higher than the REF signal, the CLKI signal will be driven high. Further, when the CLK signal is lower than the REF signal, the CLKI signal will be driven low. Conversely, the /CLKI signal is driven between a high and low level according to whether the /CLK signal is higher or lower than the REF signal. In this manner, the differential clock receivers (202 and 204) generate CLKI and /CLKI signals that are synchronous with the CLK and /CLK signals.
A drawback to memory devices, such as that set forth in FIGS. 1-3, is the added complexity required to make the various circuits within the memory device responsive to the rising edge of both the CLKI and /CLKI signals. For example, the timing and control circuit 110 could generate a first I/OCTRL signal, synchronous with the CLKI signal, and a second I/OCTRL signal synchronous with the /CLKI signal. The I/O buffer 116 would be activated by the rising edges of both the first I/OCTRL signal as well as the second I/OCTRL signals. Alternatively, the edges of both differential clock signals could be used to generate an internal clock signal at twice the frequency. Thus, although the DDR RAM 100 receives differential clock signals at one frequency, the various circuits within the DDR RAM 100 operate at twice the frequency. This is best illustrated by the DQ waveform, which shows that input data can be latched at twice the rate of the CLKS and /CLKS signals.
While the DDR RAM can provide data access rates at twice the frequency of the differential clock signals, the circuits within must be responsive to the rising edges of two clock signals. This is in contrast to conventional synchronous RAMs, which have circuits that are activated in response to the rising edge of a single clock signal. Thus, DDR RAMs can require more complex internal circuits.
It would be desirable to provide a RAM that can operate with a differential clock input, but that does not require the specialized circuits necessary to operate in synchronism with two different differential clock signals.